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CS5181 Modulator & 400 kHz to 625 kHz 16-Bit ADC
Features
l 16-Bit
Description
CS5181 is a fully calibrated high-speed analog-todigital converter, capable of 625 kSamples/second output word rate (OWR). The OWR scales with the master clock. It consists of a 5th order modulator, decimation filter, and serial interface. The chip can use the 2.375 V on-chip voltage reference, or an external 2.5 V reference. The input voltage range is 1.6 x VREFIN Vpp fully differential. Multiple CS5181s can be fully synchronized in multi-channel applications with a sync signal. The part has a power-down mode to minimize power consumption at times of system inactivity. The high speed digital I/O lines have complementary signals to help reduce radiated noise from traces on the PC board layout. The CS5181 can also be operated in modulator-only mode which provides the delta-sigma modulator bitstream as the output. ORDERING INFORMATION CS5181-BL -40 C to +85 C 28-pin PLCC
Delta-Sigma A/D Converter l Fully Differential Input with 4.0 Vpp Range l Dynamic Range: 93 dB l Spurious Free Dynamic Range: 90 dBc l Harmonic Distortion: 89 dB l Up to 625 kHz Output Word Rate l No Missing Codes l Non-Aliasing Low-Pass Digital Filter l High Speed 3-Wire Serial Interface l Supply Requirements:
- VA+ = 5 V, VD+ = 3.3 V: 570 mW
l Modulator
Output Mode l Power-Down Mode
I
VA+
AGND
VD+
DGND
AIN+ AINVREFVREF+ VREFIN x1.6
Modulator
Decimator
Clock
MCLK MCLK
Mode Selector
MFLAG
VREFOUT VREFCAP
Reference
Timing and Control
Serial Interface
SDO SDO SCLK SCLK FSO
PWDN
SYNC RESET MODE
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1999 (All Rights Reserved)
Preliminary Product Information
Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
APR `99 DS250PP1 1
CS5181
TABLE OF CONTENTS
CHARACTERISTICS/SPECIFICATIONS ............................................................ 4 ANALOG CHARACTERISTICS................................................................... 4 DYNAMIC CHARACTERISTICS ................................................................. 5 DIGITAL CHARACTERISTICS.................................................................... 5 SWITCHING CHARACTERISTICS ............................................................. 6 RECOMMENDED OPERATING CONDITIONS .......................................... 7 ABSOLUTE MAXIMUM RATINGS .............................................................. 7 GENERAL DESCRIPTION .................................................................................. 8 THEORY OF OPERATION .................................................................................. 8 Converter Initialization: Calibration and Synchronization .......................... 8 Clock Generator .......................................................................................... 9 Voltage Reference ...................................................................................... 9 Analog Input ............................................................................................. 10 Output Coding .......................................................................................... 10 Modulator-Only mode ............................................................................... 10 Instability Indicator .................................................................................... 12 Digital Filter Characteristics ...................................................................... 12 Serial Interface .......................................................................................... 12 Power Supplies / Board Layout ................................................................ 12 Power-down Mode .................................................................................... 14 PIN DESCRIPTIONS ......................................................................................... 15 PARAMETER DEFINITIONS ............................................................................. 18 APPENDIX A: CIRCUIT APPLICATIONS ......................................................... 20 PACKAGE OUTLINE DIMENSIONS ................................................................. 23
Contacting Cirrus Logic Support
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Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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TABLE OF FIGURES
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. Serial Port Timing (not to scale) .............................................................................. 6 RESET and SYNC logic and timing. ....................................................................... 8 CS5181 connection diagram for using the internal voltage reference. .................... 9 CS5181 connection diagram for using an external voltage reference. .................. 10 Modulator Only Mode Data RTZ Format. .............................................................. 11 Circuit to Reconstruct Return-to-Zero (RTZ) Data from SDO/SDO into Original Modulator Bitstream.... 11 Magnitude versus frequency spectrum of modulator bitstream (MCLK = 40.0 MHz). .............................................................................................. 11 Expanded view of the magnitude versus frequency spectrum of modulator bitstream (MCLK = 40 MHz). ................................................................................. 11 CS5181 Digital Filter Magnitude Response (MCLK = 40 MHz) ............................. 12 CS5181 Digital Filter Phase Response (MCLK = 40 MHz) ................................... 12 CS5181 System Connection Diagram ................................................................... 13 Single amplifier driving only AIN+, with AIN- held at a steady dc value ................ 20 Performance of amplifier of Figure 11 overdriving AIN+ input to the CS5181 at 3.8 VPP ............................................................................................... 20 Performance of amplifier of Figure 11 with AIN+ driven at 2.0 VPP ...................... 20 Four amplifier balanced driver. .............................................................................. 21 Performance of amplifier in Figure 14 ................................................................... 21 Performance of amplifier in Figure 14 ................................................................... 22 CS5181 Differential Non-linearity plot. (Data taken with repeating ramp) ............ 22 Histogram of DNL from Figure 17 ......................................................................... 22 CS5181 Noise Histogram, 32768 samples. ......................................................... 22
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CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = -40 to 85 C; VA+ = 5 V 5%, VD+ = 3.3 V 0.3V; AGND = DGND = 0 V; MCLK = 40.0 MHz; VREFIN = VREFOUT; MODE = VD+; Analog Source Impedance = 301 Ohms with 2200 pF to AGND; Full-Scale input Sinewave at 22 kHz; Unless otherwise noted.)
Parameter Symbol (Note 1) (Note 1) DR THD SINAD SFDR (Note 2) (Note 2) (Note 6) (Notes 2 and 5) (Note 6) (Note 2) (Note 3) CMR INL DNL Min 89 84 82 84 1 (Note 2) CMRR 50 2.25 (Note 4) 2.25 Typ 93 89 87 90 2 8 50 8 6.0 1.6 X VREFIN 4.0 300 160 2.375 1 2.375 0.1 Max 0.5 VREFIN + 0.25 320 2.6 320 2.5 500 Unit dB dB dB dBc LSB LSB LSB ppm/C LSB V/C Vpp V pF k dB A V A V A
Dynamic Performance Dynamic Range Total Harmonic Distortion @ 22 kHz Signal to (Noise + Distortion) Spurious Free Dynamic Range Static Performance Integral Nonlinearity Differential Non-Linearity Full Scale Error Full Scale Drift with Internal Reference Offset Error Offset Drift Analog Input Differential Input Voltage Range
Common Mode Range Input Capacitance Differential Input Impedance (capacitive) Common Mode Rejection Ratio Common Mode Input Current
Reference Input VREFIN VREFIN Current Reference Output VREFOUT Voltage VREFOUT Output Current VREFOUT Impedance
Notes: 1. Dynamic range is tested with a 22 kHz input signal 60 dB below full scale. 2. Specification guaranteed by design, characterization, and/or test. 3. Full scale fully-differential input span is nominally 1.6 X the VREFIN voltage. The peak negative excursion of the signals at AIN+ or AIN- should not go below AGND for proper operation. 4. VREFIN current is less than 1 A under normal operation, but can be as high as 320 A during calibration. 5. Drift of the on-chip reference alone is typically about 30 ppm/C. If using an external reference, total full scale drift will be that of the external reference plus an additional 20 ppm/C, which is the typical drift of the X1.6 buffer. 6. Applies after self-calibration at final operating ambient temperature.
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ANALOG CHARACTERISTICS (Continued)
Parameter Symbol (Note 7) PSRR 53 92.4 3.7 0.062 53 18.9 3.7 0.062 55 65 100 6 0.2 65 22 6 0.2 mA mA mA mA mA mA mA mA dB Min Typ Max Unit
Power Supplies
Power Supply Current (MODE = 1, PWDN = 1) VA1+, VA2+ = 5 V VD1+, VD2+ = 3.3 V
Power Supply Current (MODE = 1, PWDN = 0) (Notes 7, 8) VA1+, VA2+ = 5 V VD1+, VD2+ = 3.3 V Power Supply Current (MODE = 0, PWDN = 1) VA1+, VA2+ = 5 V VD1+, VD2+ = 3.3 V (Note 7)
Power Supply Current (MODE = 0, PWDN = 0) (Notes 7, 8) VA1+, VA2+ = 5 V VD1+, VD2+ = 3.3 V Power Supply Rejection (Note 9)
Notes: 7. All outputs unloaded. All inputs except MCLK held static at VD+ or DGND. 8. Power consumption when PWDN = 0 applies only for no master clock applied (MCLK held high or low). 9. Measured with a 100 mVpp sine wave on the VA+ supplies at a frequency of 100 Hz.
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Output Word Rate Symbol Min Typ MCLK MCLK/64 MCLK/142.3804 MCLK/128 2370/MCLK Max 0.05 Unit Hz Hz Hz dB Hz dB s
Filter Characteristics -3 dB Corner Passband Ripple Stopband Frequency Stopband Rejection Group Delay
(Note 2)
90 -
DIGITAL CHARACTERISTICS (TA = -40 to 85 C;
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (IO = -100 A) Low-Level Output Voltage (IO = 100 A) Input Leakage Current Input Capacitance
VD = 3.3V 0.3V; AGND = DGND = 0 V) Min 2.0 2.7 Typ 1 6 Max 0.8 0.3 10 Unit V V V V A pF
Symbol VIH VIL VOH VOL Iin Cin
Specifications are subject to change without notice.
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CS5181
SWITCHING CHARACTERISTICS (TA = -40 to 85 C; VA+ = 5 V 5%,
AGND = DGND = 0 V; MODE = VD+) Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times (Notes 2, 10, and 11) Any Digital Input, Except MCLK MCLK Any Digital Output (Notes 2, 10, and 11) Any Digital Input, Except MCLK MCLK Any Digital Output trise tfall 1/MCLK 1/MCLK 20 3 988205/MCLK 3 5161/MCLK 5168/MCLK MCLK/3 1/MCLK 2/MCLK 2/MCLK + 2E-9 1.5 1/MCLK - 2E-9 100 .2/MCLK ns s ns ns s ns s s s s Hz s s s ns s 20 100 .2/MCLK ns s ns (Note 2) Symbol MCLK Min 0.512 45 Typ 25 to 40 Max 41 55 Unit MHz % VD+ = 3.3 V 0.3 V;
Fall Times
Calibration/Sync
RESET rising to MCLK rising RESET rising recognized, to FSO falling SYNC rising to MCLK rising SYNC rising recognized to FSO falling PWDN rising recognized to FSO falling SYNC high time RESET low time
Serial Port Timing SCLK frequency SCLK high time SCLK low time FSO falling to SCLK rising SCLK falling to new data bit SCLK rising to FSO rising
(Note 12)
t1 t2 t3 t4 t5 -
Notes: 10. Rise and Fall times are specified at 10% to 90% points on waveform. 11. RESET, SYNC, and PWDN have Schmitt-trigger inputs. 12. Specifications applicable to complementary signals SCLK and SDO.
FSO t3 SCLK t4 SDATA XX MSB MSB-1 LSB-1 LSB XX t1 t2 t5
Figure 1. Serial Port Timing (not to scale)
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RECOMMENDED OPERATING CONDITIONS (AGND = DGND = 0 V)
Parameter DC Power Supplies Analog Reference Voltage AGND to DGND differential Operating Junction Temperature Tj Digital Analog Symbol VD+ VA+ VREFIN Min 3.0 4.75 2.25 -100 Typ 3.3 5 2.5 0 Max 3.6 5.25 2.6 100 120 Unit V V V mV C
ABSOLUTE MAXIMUM RATINGS
Parameter DC Power Supplies Symbol Ground AGND/DGND Digital VD+ Analog VA+ Iin Iout VINA VIND TA Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -40 -65 Max (VD+) + 0.3 6.0 6.0 10 25 1000 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V C C
Input Current, Any pin except Supplies Output Current Power Dissipation (Total) Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Specifications are subject to change without notice.
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CS5181
GENERAL DESCRIPTION
The CS5181 is a monolithic CMOS 16-bit A/D converter designed to operate in continuous mode after being reset. The CS5181 can operate in modulator-only mode in which the bit stream from the modulator is the data output from the device. The CS5181 is designed to perform conversions continuously with an output rate that is equivalent to MCLK/64. The conversions are performed and the serial port is updated independent of external controls. The converter is designed to measure differential bipolar input signals, and unipolar signals, with a common mode voltage of between 1.0 V and VREF + 0.25 V. Calibration is performed when the RESET signal to the device is released. If RESET is properly framed to MCLK, the converter can be synchronized to a specific MCLK cycle at the system level. The SYNC signal can also be used to synchronize multiple converters in a system. When SYNC is used, the converter does not perform calibration. The SYNC signal is recognized on the first rising edge of MCLK after SYNC goes high. SYNC aligns the output conversion to occur every 64 MCLK clock cycles after the SYNC signal is recognized and the filter is settled. After the SYNC is initiated by going high, the converter will wait 5,161 MCLK cycles for the digital filter to settle before putting out a fully-settled conversion word. To synchronize multiple converters in a system, the SYNC pulse should rise on a falling edge of the MCLK signal. This ensures that the SYNC input to all CS5181s in the system will be recognized on the next rising edge of MCLK. Use of the SYNC input
THEORY OF OPERATION
The front page of this data sheet illustrates the block diagram of the CS5181.
Converter Initialization: Calibration and Synchronization
The CS5181 does not have an internal power-on reset circuit. Therefore when power is first applied to the device the RESET pin should be held low until power is established. This resets the converter's logic to a known state. When power is fully established the converter will perform a self-calibration, starting with the first MCLK rising edge after RESET goes high. The converter will use 988,205 MCLK cycles to complete the calibration and to allow the digital filter to fully settle, after which, it will output fullysettled conversion words. The converter will then continue to output conversion words at an output word rate equal to MCLK/64. Figure 2 illustrates the RESET and SYNC logic and timing for the converter.
CS5181
RESET D CLK Q Q RESET
MCLK RESET FSO
MCLK MCLK SYNC D CLK
FSO
988205 MCLK Cycles
Q
SYNC SYNC
5161 MCLK Cycles
Figure 2. RESET and SYNC logic and timing.
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is not necessary to make the converter operate properly. If it is unused it should be tied to DGND. Conversion data is output from the SDO and SDO pins of the device. The data is output from the SDO pin MSB first, in two's complement format. The converter furnishes a serial clock SCLK and its complement SCLK to latch the data bits; and a data frame signal, Frame Signal Output (FSO), which frames the output conversion word. The SCLK output frequency is MCLK/3.
Voltage Reference
The CS5181 can be configured to operate from either its internal voltage reference, or from an external voltage reference. The on-chip voltage reference is nominally 2.375 V and is referenced to the AGND pins. This 2.375 V reference is output from the VREFOUT pin. It is then filtered and returned to the VREFIN pin. The VREFIN pin is connected to a buffer which has a typical gain of 1.6. This scales the on-chip reference of 2.375 V to 3.8 V. This value sets the peak-to-peak input voltage into the AIN pins of the converter. Figure 3 illustrates the CS5181 connected to use the internal voltage reference. Note that a 1.0 F and 0.1 F capacitor are shown connected to the VREFCAP pin to filter out noise. A larger capacitor can be used, but may require a longer reset period when first powering up the part to allow for the reference to stabilize before the part self-calibrates. Alternatively, the CS5181 can be configured to use an external voltage reference. Figure 4 illustrates the CS5181 connected to use a 2.5 V external reference. In this case, the maximum peak-to-peak signal input at the AIN pins is 4.0 V.
Clock Generator
The CS5181 must be driven from a CMOS-compatible clock at its MCLK pin. The MCLK input is powered from the VD+ supply and its signal input should not exceed this supply. The required MCLK is 64 x OWR (Output Word Rate). To achieve an Output Word Rate of 625 kHz, the MCLK frequency must be 64 x 625 kHz, or 40 MHz. A second clock input pin, MCLK, is not actually used inside the device but allows the user to run a fully differential clock to the converter to minimize radiated noise from the PC board layout. The CS5181 can be operated with MCLK frequencies from 512 kHz up to 40 MHz. The output word rate scales with the MCLK rate with OWR = MCLK/64.
CS5181
VREFIN VREF+ 10 F + 0.1 F VREF-
X1.6 Modulator
VREFOUT + 10 F 0.1 F VREFCAP + 1 F 0.1 F
X1
Reference
Figure 3. CS5181 connection diagram for using the internal voltage reference.
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CS5181
CS5181
VS 2.5 V 0.1 F 10 F VREFIN
+ 0.1 F
+
X1.6 Modulator
VREF+ 10 F + 0.1 F VREF-
10 F
VREFOUT + 10 F 0.1 F VREFCAP + 1 F 0.1 F
X1
Reference
Figure 4. CS5181 connection diagram for using an external voltage reference.
Analog Input
The analog signal to the converter is input into the AIN+ and AIN- pins. The input signal is fully differential with the maximum peak-to-peak amplitude of VREFIN X 1.6 V. The signal needs to have a common mode voltage in a range from 1.0 V to VREF + 0.25 V for minimum distortion. A resistor-capacitor filter should be included on the AIN+ and AIN- inputs of the converter. This should consist of a 20 resistor and a 2200 pF capacitor on each input to ground as illustrated in the system connection diagram (Figure 11).
Fully Differential Bipolar Input Voltage1 >(VFS - 1.5 LSB) VFS - 1.5 LSB -0.5 LSB -VFS + 0.5 LSB <(-VFS + 0.5 LSB)
Twos Complement 7FFF 7FFF 7FFE 0000 FFFF 8001 8000 8000
Notes: 1. VFS = VREFIN x 1.6 Table 1. Output Coding.
Output Coding
Table 1 illustrates the output coding for the converter when operating with the digital filter (MODE = 1). The converter outputs its data from the serial port in twos complement format, MSB first. The chip offers an MFLAG signal to indicate when the modulator has gone unstable. MFLAG is set when an overrange signal forces the modulator into an unstable condition. Under this condition, output
codes from the converter will be locked to either plus or minus full scale as is appropriate for the overrange condition.
Modulator-Only mode
The CS5181 can be operated in modulator-only mode by connecting the MODE pin to a logic 0 (DGND). In modulator-only mode the noise-shaped bitstream from the fifth-order delta-sigma modulator is output from the SDO and SDO (inverse bitstream) pins.
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MCLK Modulator Data SDO SDO Reconstructed Data
Figure 5. Modulator Only Mode Data RTZ Format.
The data from the modulator is output from SDO/SDO in RTZ (Return to Zero) format. The circuit in Figure 6 can be used to reconstruct the data so it can be captured with the rising or falling edge of MCLK. Table 2 illustrates the magnitude of the input signal into the chip versus the ones density out of the modulator. The table does not take into account the potential offset and gain errors of the modulator and their effect on the ones density.
Fully Differential Bipolar Input Voltage2 VFS 0 -VFS Modulator Ones Density3 75% 50% 25%
Figure 7 and Figure 8 illustrate magnitude versus frequency plots of the modulator bitstream when running at 40.0 MHz.
Notes: 2. VFS = VREFIN x 1.6 3. Ones density is approximate; it does not take offset and gain errors into consideration. Table 2. Modulator-Only Mode Ones Density.
Figure 7. Magnitude versus frequency spectrum of modulator bitstream (MCLK = 40.0 MHz).
SDO
Reconstructed Data
SDO
Reconstructed Data
Figure 6. Circuit to Reconstruct Return-to-Zero (RTZ) Data from SDO/SDO into Original Modulator Bitstream.
Figure 8. Expanded view of the magnitude versus frequency spectrum of modulator bitstream (MCLK = 40 MHz).
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Instability Indicator
The MFLAG signal is functional in both modes of operation of the part and indicates when the modulator has been overdriven into an unstable condition. In the modulator only mode (MODE = 0), the MFLAG signal will remain set for 3 MCLK cycles when the modulator goes unstable, before being returned to the reset state. While the input condition causing modulator instability persists, the MFLAG signal will continually get set for 3 MCLK cycles and then get reset. When the decimation filter on the part is operational (MODE = 1), the MFLAG signal is set when the modulator goes unstable. In this mode, however, the MFLAG signal stays set until 5,120 MCLK cycles after the input condition causing modulator instablility is removed. This delay is provided to allow the digital filter time to settle, and the part will output fully settled conversion words after the MFLAG signal goes low.
Figure 9. CS5181 Digital Filter Magnitude Response (MCLK = 40 MHz)
250.00 200.00 150.00
Phase (deg.)
100.00 50.00 0.00 -50.00 -100.00 -150.00 -200.00 -250.00
0 50k 100k 150k 200k Freq (Hz) 250k 300k
Digital Filter Characteristics
Figure 9 illustrates the magnitude versus frequency plot of the converter when operating at a 625 kHz output word rate. The filter is a non-aliasing 4265 tap filter with a -3 dB corner at 0.4495 of the output word rate and an out-of-band attenuation of at least 90 dB at frequencies above one half the output word rate. The passband ripple is less than 0.05 dB up to the -3 dB corner frequency. Figure 10 illustrates the phase response of the digital filter with the converter operating at 625 kHz output word rate. The filter characteristics change proportional to changes in the MCLK rate. The group delay of the digital filter is 2370 MCLK cycles (59.3 s with MCLK = 40 MHz), and the settling time is 4740 MCLK cycles (118.5 s).
Figure 10. CS5181 Digital Filter Phase Response (MCLK = 40 MHz)
rial Data Output pin (SDO), and its complement (SDO); Serial Clock (SCLK), and its complement (SCLK); and the Frame Sync Output (FSO). FSO falls at the beginning of an output word. Data is output in twos complement format, MSB first. FSO stays low for 16 SCLK cycles. SCLK is output at a rate equal to MCLK/3.
Serial Interface
The CS5181 has a serial interface through which conversion words are output in a synchronous selfclocking format. The serial port consists of the Se12
Power Supplies / Board Layout
The CS5181 requires an analog supply voltage of 5.0 Volts and a digital supply voltage of 3.3 Volts (nominal) for proper operation.
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Figure 11 illustrates the system connection diagram for the chip. For best performance, each of the supply pins should be bypassed to the nearest ground pin on the chip. The bypass capacitors should be located as close to the chip as possible. If the chip is surface mounted the bypass capacitors should be on the same side of the circuit card as the chip. The CS5181 is a high speed component that requires adherence to standard high-frequency printed circuit board layout techniques to maintain optimum performance. These include the use of ground and power planes, using low noise power supplies in conjunction with proper supply decoupling, minimizing circuit trace lengths, and physical separation of digital and analog components and circuit traces. It is preferred that any clock oscillator circuitry be located on a ground plane separate from the digital plane in order to ensure that digital noise does not induce clock jitter. For additional insight, see the CDB5181 evaluation board for more details. Also refer to Application Note AN18 which covers layout and design rules for high resolution data converters.
1 0.1 F
AGND1
DGND1
22 0.1 F
+5 V
28 8
VA1+
VD1+
21 12
+3.3 V
VA2+
CS5181
VD2+
0.1 F
7 18
AGND2
DGND2
11
0.1 F
AGND3 PWDN MODE RESET SYNC MFLAG VREF+ MCLK 20 19 25 24 23 10 9
4 + 10 F 0.1 F 5 3 2 + 10 F 0.1 F 6 + 1 F 20 0.1 F
26
VREFOUT
VREFIN VREF-
Control Logic
MCLK
VREFCAP
Clock Source
AIN+
3.8 Vpp Fully Differential ~ CMV = 2.375 V
FSO SCLK SCLK SDO SDO
17 14 13 16 15 Data Interface
2200 pF 20 2200 pF 27 AIN-
The 3.8 Vpp fully differential input span is set by the converter's internal voltage reference at 2.375 V. An input span of 4.0 Vpp fully differential would result if an external voltage reference of 2.5 V is used.
Figure 11. CS5181 System Connection Diagram
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Power-down Mode
The CS5181 has a PWDN (power-down) function. When active low, power to most of the converter's circuitry will be reduced. If MCLK is to be stopped to save power, it should not be stopped until at least ten clock cycles after PWDN is taken low. The ten clock cycles are required to allow the part to turn off it's internal circuitry. If the part does not get the full ten clock cycles, it will still go into a power down state, but the power dissipation could be more than is listed in the specifications for the full power down condition. When PWDN is active, the calibration information inside of the converter is maintained. When coming out of the power-down state, the converter is not recalibrated and will start-up similar to when SYNC is initiated.
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PIN DESCRIPTIONS
Analog Ground Pos. Reference Neg. Reference Pos. Reference Input Analog Ground Analog Supply Invalid Conversion Sync. Filter Digital Ground Pos. Digital Supply Inverse Serial Clock Serial Clock AGND VREF+ VREFVREFIN
5 6 7 8 9 10 11 12 13 14 15 16 17 18 43
VA1+ AINAIN+ PWDN
2 1 28 27 26 25 24
Positive Analog Supply Negative Analog Input Positive Analog Input Power Down Mode Modulator Only Mode Digital Ground Positive Digital Supply Master Clock Inverse Master Clock Analog Ground Frame Sync Output Serial Data Out Inverse Serial Data Out\ Analog Ground Positive Analog Supply Analog Ground Negative Analog Input Positive Analog Input Analog Ground Power Down Mode Modulator Only Mode Digital Ground Digital Ground Positive Digital Supply Positive Digital Supply Digital Ground Master Clock Inverse Master Clock Digital Ground Analog Ground Frame Sync Output Serial Data Out Inverse Serial Data Out\
Reference Output VREFOUT Reference Bypass VREFCAP AGND VA2+ MFLAG SYNC DGND VD2+ SCLK SCLK
MODE DGND VD1+ MCLK MCLK AGND FSO SDO SDO AGND
RESET Reset and Calibration
CS5181
23 22 21 20 19
Analog Ground Pos. Reference Neg. Reference Analog Ground Analog Ground Reference Input Analog Ground Analog Ground Analog Supply Analog Supply Invalid Conversion Sync. Filter Digital Ground Digital Ground Pos. Digital Supply Pos. Digital Supply Digital Ground Inverse Serial Clock Serial Clock
AGND VREF+ VREFAGND AGND VREFIN
4443424140393837363534 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23
VA1+ AGND AINAIN+ AGND PWDN MODE DGND DGND VD1+ VD1+ DGND MCLK MCLK DGND NC AGND NC FSO SDO SDO
Reference Output VREFOUT
Reference Bypass VREFCAP AGND AGND VA2+ VA2+ MFLAG SYNC DGND DGND VD2+ VD2+ DGND SCLK SCLK
RESET Reset and Calibration
CS5181
12131415 16171819202122
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Supply Inputs VA1+, VA2+ -- Positive Analog Supply Input for the positive analog supply is +5.0 V typical when AGND is 0 V. AGND -- Analog Ground Analog ground for circuits supplied by VA+. VD1+, VD2+ -- Positive Digital Supply Input for positive digital supply is +3.3 V typical when DGND is 0 V. DGND -- Digital Ground Digital ground for circuits supplied by VD+. Signal and Reference Related Inputs AIN+, AIN- -- Differential Analog Inputs Fully differential signal inputs. VREFIN -- Voltage Reference Input VREFOUT or an external reference is connected to VREFIN. Analog input voltage (full scale fully differential peak-to-peak) into the converter is 1.6 times this value. VREF+ -- Positive Voltage Reference Filter capacitor connection for the reference input buffer. The voltage on this pin equals VREFIN X 1.6. VREF- -- Negative Voltage Reference VREF- is connected to AGND. VREFOUT -- Voltage Reference Output Output pin for the 2.375 volt on-chip reference relative to AGND. VREFCAP -- Reference Bypass Filter capacitor connection for internal reference. Serial Interface I/O Signals SCLK, SCLK -- Serial Interface Clock Serial Clock Output. A gated serial clock output from the converter at a rate equal to 1/3 the MCLK clock rate. The SCLK output is a complement of SCLK and helps reduce radiated noise if the two lines are run adjacent on the PC board layout and drive a balanced load.
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CS5181
SDO, SDO -- Serial Data Out Serial Data Output. Output pin for 16-bit serial data word. The SDO output is the complement of SDO and helps to reduce radiated noise if the two lines are run adjacent on the PC board layout. Output data is output in twos complement format MSB first. FSO -- Frame Sync Output Frame Sync Output. The Frame Sync Output turns low to indicate the beginning of an output word from the SDO pin. It returns high after the 16 data bits have been clocked out. Control Pins RESET -- Reset and Calibration When the RESET pin is pulled to a logic low the converter will perform a reset of its digital logic. When the level on this pin is brought back to a logic high the chip starts normal operation, following a two clock cycle delay period. When MODE = 1, the chip goes through an internal gain and offset calibration routine following this reset sequence. PWDN -- Power Down Mode A logic 0 on the PWDN pin will put the device into a power-down mode. MODE -- Modulator Only Mode MODE is held at a logic high for normal operation. In normal operation the device utilizes the digital decimation filter and calibration ciruitry. MODE = 0 puts the part in modulator only mode whereby most of the digital circuitry is powered-down and the modulator bit-stream is output from the SDO and SDO pins. SYNC -- Synchronization of Filter The SYNC input can be used to restart the digital filter of the converter at the beginning of its convolution cycle. The SYNC input is used to synchronize the filters of multiple converters in a system. When the SYNC signal goes high, the filter will be initialized and will begin its convolution cycle on the next rising edge of MCLK. If not used, tie SYNC to DGND. MFLAG -- Invalid Conversion Flag MFLAG goes high if the modulator portion of the converter goes unstable. If MFLAG is high, the output data from the converter may be invalid. MCLK, MCLK -- Master Clock Signal Master clock input accepts a CMOS level clock input to the converter with worst case duty cycle of 45-55% (typically 40 MHz). MCLK is not actually used inside the device, but can be used for radiated noise cancellation if MCLK and MCLK are run adjacent to each other on the PC board.
DS250PP1
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CS5181
PARAMETER DEFINITIONS
Differential Non-Linearity Error - DNL The deviation of a code's width from ideal. Units in LSBs. Integral Non-Linearity Error - INL The deviation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 1/2 LSB below the first code transition and "full-scale" is a point 1/2 LSB beyond the code transition to all ones. The deviation is measured from the middle of each particular code. Units in LSB's. Full-Scale Error - FSEP The deviation of the last code transition from the ideal (VREF-3/2 LSB's). Units in LSB's. Offset Error - VOS The deviation of the mid-scale transition from the ideal (1/2 LSB below 0 Volts). Units in LSB's. Spurious-Free-Dynamic-Range - SFDR The ratio of the rms value of the full-scale signal, to the rms value of the next largest spectral component (excepting dc). This component is often an aliased harmonic when the signal frequency is a significant proportion of the sampling rate. Units in dBc (decibels relative to the carrier). Total Harmonic Distortion - THD The ratio of the rms sum of the significant harmonics (2nd thru 7th), to the rms value of the full-scale signal. Units in decibels. Dynamic Range - DR The ratio of the rms value of the inferred full-scale signal, to the rms sum of the broadband noise signals below the Nyquist rate (excepting dc and distortion terms). Expressed in decibels. Dynamic Range is tested with a 22 kHz input signal 60 dB below full scale. 60 dB is then added to the resulting number to refer the noise level to the full-scale signal. This technique ensures that the distortion components are below the noise level and do not affect the measurement. Signal-to-Noise-and-Distortion (s/[n+d]) - SINAD The ratio of the rms value of the full-scale signal, to the rms sum of all other spectral components below the Nyquist rate (excepting dc), including distortion components. Expressed in decibels. Group Delay The time delay through the digital filter section of the part. Units in seconds.
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DS250PP1
CS5181
Resolution - N The number of different output codes possible. Expressed as N, where 2N is the number of available output codes. Noise A measure of the variability of the converter's output when a fixed DC input (usually ground) is applied to the input and a large number of samples are taken. RMS noise is determined statistically as the Standard Deviation of the Probability Density Function derived from the histogram of the ADC with the differential inputs shorted together and tied to an appropriate common mode voltage. Common Mode Rejection Ratio - CMRR A measure of the device's ability to cancel out the effect of a common voltage applied to both of its differential inputs. CMRR is specified as the ratio of the differential signal gain to the gain for the common-mode signal. Units in dB. Offset Drift Changes in the offset error of the part after self calibration due to changes in ambient temperature. Specified in microvolts per degree C, relative to the input signal. Full Scale Drift Changes in the full scale error of the part after self calibration due to changes in ambient temperature. Specified in parts-per-million (PPM) of the full scale range per degree C.
DS250PP1
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CS5181
APPENDIX A: CIRCUIT APPLICATIONS
Several amplifier circuits have been tested with the CS5181. Performance at higher frequencies is generally limited by the operational amplifiers used to drive the A/D converter. Figure 12 illustrates a single operational amplifier circuit which can accept a single-ended ground-referenced signal and condition it for the input of the CS5181. The amplifier is AC-coupled to the signal source. In this circuit the AIN- input to the CS5181 is held at a constant DC value and the AIN+ input is driven (it is actually overdriven to achieve high dynamic range, but this sacrifices performance with regard to distortion). The common mode voltage for the CS5181 input should be designed to stay between 1 V and VREF + 0.25 V when driven at its AIN+ and AIN- inputs. The single amplifier circuit in figure 12 has the disadvantages that the common mode restriction limits the input signal range and also causes errors due to variation in the common mode voltage, as opposed to applying a balanced differential signal. Figures 13 and 14 illustrate the performance of the amplifier of Figure 12 operating with a 3.8 Vpp input into the AIN+ input; and with 2.0 Vpp input into the AIN+ input respectively.
Figure 13. Performance of amplifier of Figure 12 overdriving AIN+ input to the CS5181 at 3.8 VPP
Test Signal: 30.14 kHz @ -6 dB S/N = 85.46 dB S/D = 71.25 dB S/N+D = 71.09 dB 8192 Samples
Figure 14. Performance of amplifier of Figure 12 with AIN+ driven at 2.0 VPP
+15
0.1 F 0.15 C0G + 10 k 10 k U1 +
20 AIN+ 2200 pF 0.1 F
CS5181
-15
20
AIN-
2200 pF 1 k 10 F + 5 k 0.1 F + 10 F VREFOUT
Figure 12. Single amplifier driving only AIN+, with AIN- held at a steady dc value
20
DS250PP1
CS5181
2 k +15 V +15 V
0.1 F U1 + 10 k -15 V 2 k +15 V +15 V 2 k U2 0.1 F
2 k U3 + 0.1 F -15
0.1 F
301 AIN2200 pF
CS5181
0.1 F 2 k 2200 pF
100
2 k
-
0.1 F U4 +
301 AIN+
+ -15 V
0.1 F
-15 V
0.1 F 10 k VREFOUT
10 F 10 k
+
Figure 15. Four amplifier balanced driver.
Figure 15 illustrates a four amplifier circuit which gives the best performance by keeping everything balanced. Performance is generally limited by the amplifiers. Again, the output resistors are used to scale down the input signal. Figures 16 and 17 illustrate the performance of the CS5181 with this amplifier circuit. Figure 18 illustrates a Differential Non-linearity plot of the converter. Data for the plot was taken using a repeating ramp. Figure 19 is a histogram of the DNL data in Figure 18. Figure 20 illustrates a noise histogram of the converter with its inputs shorted and connected to a proper common mode voltage.
Test Signal: 20 kHz @ 0 dB S/N = 93.2 dB S/D = 88.6 dB S/N+D = 87.2 dB 8192 Samples
Figure 16. Performance of amplifier in Figure 15
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CS5181
Test Signal: 60 kHz @ 0 dB S/N = 92.0 dB S/D = 85.9 dB S/N+D = 85.0 dB 8192 Samples
Figure 17. Performance of amplifier in Figure 15
Figure 18. CS5181 Differential Non-linearity plot. (Data taken with repeating ramp)
Figure 19. Histogram of DNL from Figure 18
Figure 20. CS5181 Noise Histogram, 32768 samples.
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DS250PP1
CS5181
PACKAGE OUTLINE DIMENSIONS
28L PLCC PACKAGE DRAWING
e D2/E2
E1 E
B
D1 D A
A1
INCHES DIM A A1 B D D1 D2 E E1 E2 e MIN 0.165 0.090 0.013 0.485 0.450 0.390 0.485 0.450 0.390 0.040 MAX 0.180 0.120 0.021 0.495 0.456 0.430 0.495 0.456 0.430 0.060
MILLIMETERS MIN MAX 4.043 4.572 2.205 3.048 0.319 0.533 11.883 12.573 11.025 11.582 9.555 10.922 11.883 12.573 11.025 11.582 9.555 10.922 0.980 1.524
JEDEC # : MS-018
DS250PP1
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